• cpu-design
Nearly Doubling My CPU's Clock Speed by Removing Complexity
How simplifying my instruction fetch path improved Fmax from ~25 MHz to ~45 MHz on my custom dual-issue CPU.
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System.init(mode="ENGINEERING")
Designing Modern Compute.
I'm Dulat. I like taking ideas all the way from scratch code to something that actually runs: custom CPU cores, emulators, tools, and backend services.
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Custom Architecture
NeoCore 16x32 CPU
My custom CPU project: a 16-bit ISA with a 5-stage, in-order, dual-issue microarchitecture written in SystemVerilog, backed by a C/C++ emulator and assembler/linker.
- 16-bit instruction set designed from scratch
- C/C++ emulator plus assembler/linker toolchain
- 5-stage, in-order pipeline with dual-issue support
NEOCORE16×32 ISA
Dual-issue
5-stage pipeline
Projects
Software & Systems Work
Not everything I do is CPU design. I also write a lot of C/C++ and backend code, build small tools, and experiment with systems that sit closer to real-world use.
Backend & APIs
C/C++ and web backends for small services and apps, with a focus on clear interfaces and reliability over cleverness.
Developer Tools
Utility scripts, CLIs, and helpers that support my CPU and systems work: testing harnesses, build tooling, and debugging helpers.
Emulators & Simulators
Cycle-ish level emulators to prototype ISAs and behavior before committing to hardware.
Future Hardware Integration
Long-term goal: tie my CPU and software work into real embedded/avionics-style stacks when the hardware is ready.
Workflow
How I Build Things
Roughly how a project goes for me, from idea to something I can actually run, test, and break.
1
Design
Figuring out the ISA, architecture, or system boundaries on paper before touching code.
2
Core Implementation
C/C++ for emulators and tools, SystemVerilog for hardware, plus small support programs when needed.
3
Testing
Writing tests, running programs end-to-end, and checking behavior against what I intended, not what I assumed.
4
Iteration
Refactoring, simplifying, and fixing whatever falls over under real use.
5
Integration
Connecting pieces together: toolchains, small services, and (eventually) real hardware targets.
Lab Log
Recent Notes 2025
Shipped NeoCore 16x32 v0.1.0
First full loop working: custom ISA, emulator, assembler/linker, and SystemVerilog microarchitecture reaching v0.1.0.
2024
Ongoing Assembler & Tooling Work
Improving the assembler/linker and general build flow so adding new instructions and tests doesn’t suck.
2023
Foundation Early Emulator Experiments
Started with simple emulators and small programs to get comfortable with instruction sets and control flow at a low level.