Development of NeoCore16x32 is finished

After ~3+ years, NeoCore16x32 is “done” in the sense that the core works end-to-end:

• ISA + assembler/linker
• Synthesizable RTL
• Simulation/profiling flow
• FPGA build

I have achieved real measured results: 25.0388 MHz on ULX3S-85F, delivering ~23 MIPS (0.825 dMIPS).

What is not “done” is feature completeness. I stopped before adding the classic OS-enabling pieces:

• Stack/subroutine support
• Interrupts
• A real external bus/peripheral story

So it’s a complete reference implementation of the architecture I did implement, but not a complete “computer platform.”

Resources

• Source Code: github.com/dulatello08/cpu-v01
• White Paper: Read the PDF

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