Development of NeoCore16x32 is finished

After ~3+ years, NeoCore16x32 is “done” in the sense that the core works end-to-end:

• ISA + assembler/linker
• Synthesizable RTL
• Simulation/profiling flow
• FPGA build

I have achieved real measured results: 25.0388 MHz on ULX3S-85F, delivering ~23 MIPS (0.825 dMIPS).

V1 achieved its core goal: a fully functioning reference architecture running real benchmarks on bare metal. The important part is that the ISA, toolchain, RTL, simulation flow, and FPGA path all close the loop into something measurable.

Resources

• Source Code: github.com/dulatello08/cpu-v01
• White Paper: Read the PDF

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