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Uncovering Black Boxes.

I'm Dulat. I build systems that are close to electrons: custom RTL CPU cores, compilers, assemblers, linkers and bare-metal tools.

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Custom Architecture

NeoCore 16x32 CPU

My first end-to-end CPU system: a 16-bit ISA with a dual-issue, 7-stage in-order pipeline written in SystemVerilog, along with supporting infrastructure: an emulator and assembler/linker.

  • 16-bit instruction set designed from scratch
  • C/C++ emulator plus assembler/linker toolchain
  • 7-stage, in-order pipeline with dual-issue support
  • FPGA build closes on ULX3S-85F with measured 25.0388 MHz
Open NeoCore 16x32 project
NEOCORE16×32 ISA
Dual-issue
7-stage pipeline
NEOCORE-FX32-bit ISA
0.575 DMIPS/MHz
6-stage / ULX3S
Second CPU Project

NeoCore-FX CPU

My more recent NeoCore system where the software stack gets more complexity. It is a single-issue, 6-stage in-order pipeline written in SystemVerilog. FX goes tightly along with a custom LLVM backend, advanced assembler/linker support, and a newer FPGA flow.

  • SystemVerilog RTL targeting Lattice ECP5 and ULX3S-85F
  • LLVM backend, assembler, linker, and compiler wrapper work
  • Stable Dhrystone sweep at about 0.575 DMIPS/MHz
  • UART MMIO, simulation workflows, FPGA builds, and optional hardware debug support
Open NeoCore-FX project

Beyond the projects

01

Robotics club president

Leading my school's robotics club and competing in FTC-style engineering environments.

02

Science Olympiad

Competition results that show technical curiosity beyond one long-running personal project.

03

Pool Guard II, swim instructor, and water-polo coach

City of San Diego Pool Guard II; I teach swim lessons and coach a recreational water polo team.

Photo / 01
Robotics club president
Photo / 02
Science Olympiad
Photo / 03
Pool Guard II, swim instructor, and water-polo coach