Robotics club president
Leading my school's robotics club and competing in FTC-style engineering environments.
I'm Dulat. I build systems that are close to electrons: custom RTL CPU cores, compilers, assemblers, linkers and bare-metal tools.
My first end-to-end CPU system: a 16-bit ISA with a dual-issue, 7-stage in-order pipeline written in SystemVerilog, along with supporting infrastructure: an emulator and assembler/linker.
My more recent NeoCore system where the software stack gets more complexity. It is a single-issue, 6-stage in-order pipeline written in SystemVerilog. FX goes tightly along with a custom LLVM backend, advanced assembler/linker support, and a newer FPGA flow.
The software layer for NeoCore-FX: LLVM backend, assembler and linker. It is a pipeline that turns C or assembly into binary that NeoCore CPUs can run.
An out-of-tree LLVM target for NeoCore-FX that compiles C programs in LLVM IR, which are lowered to NeoCore-FX assembly through llc. Features a small backend-focused repository and clang-like wrapper.
View projectnc-as is the assembler for the NeoCore family. It emits object files in a custom format, supports relocations, preprocessor features, and assembles output from both nc-cc and the FX LLVM backend.
View projectnc-ld is the linker. It links custom LF02 object files into flat memory images and handles address relocations. This makes it the bridge between compiler output and binaries that can run on the CPU cores.
View projectLeading my school's robotics club and competing in FTC-style engineering environments.
Competition results that show technical curiosity beyond one long-running personal project.
City of San Diego Pool Guard II; I teach swim lessons and coach a recreational water polo team.
After 3+ years, the NeoCore16x32 CPU reference implementation is complete.
Exploring the custom SAMD21 firmware for the Neodrone flight controller.
A look at the Stretched-X PCB Frame design in 3D.