LLVM backend
C to NeoCore-FX assembly
The backend turns NeoCore-FX into a compiler target and connects architecture decisions directly to code generation.
Project 2 / Software + Toolchain
NeoCore-FX CPU + LLVM Toolchain
A newer NeoCore path with a more advanced software stack: single-issue 6-stage RTL, LLVM backend work, assembler/linker support, compiler wrapper, simulation flows, and FPGA bring-up work.
Design focus
The complete software path: LLVM lowering, assembly, linking, memory images, and repeatable benchmark runs on a custom CPU target.
Core
Single-issue
Pipeline
6-stage
Benchmark
0.575 DMIPS/MHz
Target
ECP5 / ULX3S
What it is
NeoCore-FX pushes the black-box question upward: once the CPU exists, how does C become machine code for it? This project connects RTL with compiler backend work, object files, linking, memory images, and measured runs.
Active project with stable Dhrystone sweep numbers and toolchain integration work in progress.
Measured results
- SystemVerilog RTL targeting Lattice ECP5/ULX3S-85F
- Out-of-tree LLVM backend lowering LLVM IR toward NeoCore-FX assembly
- Assembler and linker pipeline for object files and memory images
- Stable Dhrystone sweep around 0.575 DMIPS/MHz
- UART MMIO, simulation workflows, FPGA builds, and optional debug support
Development notes
- Kept the core simpler than NeoCore 16x32 so the compiler/toolchain path could advance
- Built the backend and assembler/linker path around actual binaries instead of isolated code snippets
- Reran benchmark sweeps end-to-end to avoid relying on one-off numbers
- Separated canonical-safe flags from optimization-level experiments
Assembler and linker
Assembly to runnable images
nc-as and nc-ld bridge compiler output to flat memory images, including object files, relocations, scripts, and the practical details needed to run programs on the core.