Selected Work

Systems I built, measured, and ran.

Two custom CPU paths, the software around them, and the work I do with teams beyond code.

Hardware
Completed V1

NeoCore 16x32 CPU

A custom 16-bit ISA and 7-stage, in-order, dual-issue SystemVerilog CPU with its own emulator, assembler/linker, and ULX3S-85F FPGA build.

  • Dual-issue microarchitecture
  • FPGA build closes at 25.0388 MHz
  • Whitepaper and source available
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Software + Toolchain
Active

NeoCore-FX + Toolchain

A newer CPU path where the software stack is more advanced: RTL, LLVM backend, assembler, linker, compiler wrapper, simulation workflows, and measured Dhrystone runs.

  • LLVM backend work
  • Assembler/linker pipeline
  • Stable Dhrystone around 0.575 DMIPS/MHz
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Leadership + Service
Beyond code

Robotics, SciOly, and Aquatics

Robotics club leadership, Science Olympiad competition, and work as a City of San Diego Pool Guard II, swim instructor, and recreational water-polo coach.

  • Team leadership
  • Science Olympiad competition
  • Operational responsibility under pressure
View beyond projects