Project 1 / Hardware Architecture
NeoCore 16x32 CPU
A custom CPU project centered on hardware architecture: a 16-bit ISA, C/C++ emulator, assembler/linker, and 7-stage in-order dual-issue SystemVerilog implementation that compiles for an ULX3S-85F FPGA.
Design focus
A seven-stage, dual-issue microarchitecture connects the custom ISA to an FPGA-targeted SystemVerilog implementation.
Issue model
Dual-issue
Pipeline
7-stage
FPGA
ULX3S-85F
Measured close
25.0388 MHz
What it is
I wanted to understand what a CPU actually is underneath the abstraction. NeoCore 16x32 is the answer: I designed the instruction set, built the software tools around it, and implemented the processor in RTL instead of stopping at a simulator.
V1 achieved its core goal: a working reference architecture with custom ISA, emulator, assembler/linker, and FPGA-targeted RTL.
Measured results
- Custom 16-bit instruction set
- SystemVerilog RTL for a 7-stage in-order dual-issue CPU
- C/C++ emulator for architecture bring-up
- Assembler/linker support for running programs
- FPGA build closes on ULX3S-85F
Development notes
- Designed the ISA and architecture boundaries before RTL
- Used emulator/tooling to validate behavior before committing to hardware
- Iterated on pipeline behavior until it matched the intended execution model
- Packaged the work into a whitepaper and public project page